In the family of electrically programmable nonvolatile semiconductor memory devices, FLOTOX (Floating-gate Tunneling Oxide) EEPROM memory devices are known having memory cells comprising floating-gate MOSFETs; an EPROM memory cell is in fact composed of a floating-gate MOSFET and a selection transistor. Each floating-gate MOSFET comprises an N type source region and an N type drain region formed spaced-apart inside a P type semiconductor substrate or well. The portion of the P type substrate or well comprised between the source and drain regions forms a channel region. A floating gate electrode (formed by means of a first level of polysilicon) is placed above the channel region and part of the drain region with the interposition of a gate oxide layer. In correspondence of the drain region, the gate oxide has a thinner area called tunnel oxide. A control gate electrode (formed by means of a second level of polysilicon) is insulatively placed above the floating gate electrode.
The selection transistor of the memory cell is connected in series to a respective floating-gate MOSFET and is used for enabling the memory cell to engage in read and write operations.
Writing of information in the memory cell means the removal of electrons from the floating gate; once the selection transistor is activated, a sufficiently high positive voltage is applied to the drain, while the source is left floating. The control gate and the substrate are kept at ground. Electrons tunnel from the floating gate to the drain. In a written memory cell, during the read operation a current flows in the channel.
In order to erase the datum in the memory cell, the floating gate of the MOSFET is negatively charged by means of the Fowler-Nordheim (F-N) tunneling of electrons from the drain through the tunnel oxide. This is achieved by applying a sufficiently high positive voltage to the control gate of the cell, while the source, the drain and the substrate are kept at ground. In a successive read operation, when the memory cell is selected, no current will flow in the channel.
As known, double polysilicon level FLOTOX EEPROM memory devices comprise a matrix of memory cells (memory matrix) comprising an arrangement of memory cells located at the intersections of rows ("word lines") and columns ("bit lines").
In these devices it is possible to write a single memory cell and to erase groups of eight cells forming a byte of information. The control gates of the eight cells are in fact connected to each other by means of a word line formed by a strip of the second level of polysilicon. The word lines are physically separated for each byte, while the drain regions of the selection transistors of the cells belonging to a same column are connected to each other by means of a bit line generally formed by a metal strip. The source regions of the memory cells are generally formed by a common diffusion for all the cells of the matrix.
During the reading of the memory cells, the read current causes a voltage drop across the source diffusion due to the resistance of thereof. The effective source voltage of the memory cells farther from the contact between the source diffusion and a metal strip supplying the necessary voltages will therefore be different with respect to the cells near the source contact, due to the aforementioned voltage drop, and this alters the parameters for deciding if the information is stored in the memory or not, thus reducing the memory reliability.
This drawback is more evident in EEPROM memories providing for parallel read. in which at each read operation eight cells are selected. However, this problem also affects serial-reading EEPROM memory devices or memory devices different from EEPROM, such as for example the EPROM or Flash-EEPROM memory devices, which are also formed in matrix form and wherein each memory cell comprises a floating-gate MOSFET formed in a P type substrate or well wherein an N type source region and an N type drain region are implanted in a spaced-apart way so as to form a channel region, a floating gate electrode is disposed over the channel with the interposition of an oxide layer, and a control gate electrode is insulatively located above the floating gate electrode. The drain regions of the floating-gate MOSFETs are directly connected to respective bit lines, and a single source diffusion connects all the memory cells. Also in this case, the voltage drop across the source diffusion makes the effective source voltage of the memory cells different from cell to cell.